The internet has inspired the growth and permeation of electronics into everything from coffee machines to automobiles, hand‐held devices, mobile smart phones, healthcare monitoring and treatment equipment, communication devices, high‐end servers and more. Most of these are “always on,” and require the systems on chip (SoC) that drive the electronics to be:
- reliable
- power efficient
- high in performance
- low in cost
Functional verification of an SoC alone does not guarantee reliable silicon performance in the field. Lack of power integrity during static and dynamic operations of an SoC will result in unreliable behavior. In advanced process technologies such as FinFETs, higher current density on thinner wires lead to electromigration issues resulting in failure over time. Thermal effects can adversely affect voltage and current characteristics, further impacting device operation — not acceptable for many applications, especially automotive and healthcare. With power and performance being mostly orthogonal to each other, ensuring the integrity and reliability of the power delivery network within an SoC requires many scenario‐based analyses. To achieve adequate coverage of scenarios, one needs a fast and accurate solution.
The enhanced distributed machine processing (DMP) capability of ANSYS RedHawk provides the required capacity and performance for power and reliability analyses using a minimal memory footprint.
By distributing the extraction and simulation over multiple cores and machines, a significant gain in overall productivity is achieved. This enables higher productivity, better quality of design, and achievement of the primary requirements: power and performance, cost and time‐to‐market.
If you’d like to learn more, I invite you to attend our upcoming webinar and discover how ANSYS RedHawk can help you to meet these challenges, with a focus on power integrity and reliability of advanced networking application-specific integrated circuits (ASICs). Learn how RedHawk’s capabilities in DMP (distributed machine processing), CPA (chip package analysis), CTA (chip thermal analysis) and thermal-aware EM (electromigration) analyses can provide a total productivity gain of up to 10x in networking chip design.
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