Product development of today’s complex mobile and IoT devices requires the cooperation of independent design teams working at the chip, package, and system level. However, several roadblocks in the electronics design flow make this cooperation very difficult, impacting time, effort, and ultimately the cost required to deliver a successful product to market.
These roadblocks are due to chip, package and system design teams working in distinctly different design silos, regardless of whether they are from the same company or from multiple companies around the world. The availability of accurate chip models, package and PCB models, and a mechanism to facilitate electrical, thermal, and mechanical data exchange have been bottlenecks to understanding multiphysics effects of power consumption, thermal impact, and structural reliability.
Now, as companies drive to innovate rapidly in the IoT, automotive, aerospace, and medical industries, where low power and cost are paramount, these roadblocks have to be addressed allowing designers to innovate without borders, bridging traditional gaps between chip, package, and system, as well as between electrical, thermal, and mechanical analysis.
At DesignCon 2016, ANSYS technical experts will be sharing the floor with designers from QLogic and Avago as they share their best practices for overcoming design challenges in signal integrity and power integrity.
Users can see demos showing different aspects of the Chip-Package-System Design flow with sneak peek look at ANSYS 17.0 and listen to daily technical presentations and speak to our technical experts in the booth.
Chip package system solutions are a key focus of our development, and it’s been an exciting ride as we worked closely with our customers to empower them with solutions to optimize cell phones, cars, satellites, pacemakers and even rocket ships. We invite you to visit us at DesignCon and bring your technical challenges to discuss with our team.
Demos at DesignCon 2016
Signal-Integrity, Power-Integrity and EMI
Don’t miss this demonstration devoted to signal-integrity, power-integrity and EMI issues. Learn about unique layout assembly capability from ANSYS to integrate IC package layout, interposers, connectors, ribbon cables, flex cables and printed circuit board layout all within a single assembly. We will also display our new ultra-fast chip package analysis (CPA) solver available within ANSYS SIwave.
Thermal Efficiency and Mechanical Reliability
Thermal impact on the package is a key driver for material selection, cooling and form-factor decisions which ultimately determine the size, weight and cost of the final product. Discover how ANSYS delivers a new automated thermal analysis in ANSYS SIwave that streamlines EM–thermal coupled analysis and links to ANSYS Mechanical to predict structural impact on the electronic package.
Electrostatic Discharge
Electrostatic discharge concerns which become more challenging as device geometries get smaller and oxide layers become thinner. ANSYS delivers accurate, foundry-certified chip-level ESD solutions that enable you to detect interconnect weakness in ESD discharge paths and ensure ESD integrity and reliability from IP to SoC.
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